70592C datasheet(31/314 Pages) MICROCHIP

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DS70592C-page 31

PIC24HJXXXGPX06A/X08A/X10A

CORCON: CORE CONTROL REGISTER

U-0

—

bit 15

bit 8

U-0

R/C-0

R/W-0

U-0

—

—IPL3(1)

PSV

—

bit 7

bit 0

Legend:

C = Clear only bit

R = Readable bit

W = Writable bit

-n = Value at POR

‘1’ = Bit is set

0’ = Bit is cleared

‘x = Bit is unknown

U = Unimplemented bit, read as ‘0’

bit 15-4

Unimplemented: Read as ‘0’

bit 3

IPL3: CPU Interrupt Priority Level Status bit 3(1)

1 = CPU interrupt priority level is greater than 7

0 = CPU interrupt priority level is 7 or less

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space

0 = Program space not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

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