70592C datasheet(155/314 Pages) MICROCHIP

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DS70592C-page 155

PIC24HJXXXGPX06A/X08A/X10A

14.0 INPUT CAPTURE

The input capture module is useful in applications

requiring frequency (period) and pulse measurement.

The

PIC24HJXXXGPX06A/X08A/X10A

devices

support up to eight input capture channels.

The input capture module captures the 16-bit value of

the selected Time Base register when an event occurs

at the ICx pin. The events that cause a capture event

are listed below in three categories:

• Simple Capture Event modes:

- Capture timer value on every falling edge of

input at ICx pin

- Capture timer value on every rising edge of

input at ICx pin

• Capture timer value on every edge (rising and

falling)

• Prescaler Capture Event modes:

- Capture timer value on every 4th rising

edge of input at ICx pin

- Capture timer value on every 16th rising

edge of input at ICx pin

Each input capture channel can select between one of

two 16-bit timers (Timer2 or Timer3) for the time base.

The selected timer can use either an internal or

external clock.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

• 4-word FIFO buffer for capture values

- Interrupt optionally generated after 1, 2, 3 or

4 buffer locations are filled

• Input capture can also be used to provide

additional sources of external interrupts.

FIGURE 14-1:

INPUT CAPTURE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24HJXXXGPX06A/X08A/X10A

family of devices. However, it is not

intended to be a comprehensive refer-

ence source. To complement the infor-

mation in this data sheet, refer to the

“dsPIC33F/PIC24H Family Reference

Manual”, Section 12. “Input Capture”

(DS70248), which is available from the

Microchip website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

Only IC1 and IC2 can trigger a DMA data

transfer. If DMA data transfers are

required, the FIFO buffer size must be set

to 1 (ICI<1:0> = 00).

ICxBUF

ICx Pin

ICM<2:0> (ICxCON<2:0>)

Mode Select

Set Flag ICxIF

(in IFSn Register)

TMRy TMRz

Edge Detection Logic

FIFO

R/W

Logic

ICxI<1:0>

ICOV, ICBNE (ICxCON<4:3>)

ICxCON

Interrupt

Logic

System Bus

From 16-bit Timers

ICTMR

(ICxCON<7>)

Prescaler

Counter

(1, 4, 16)

and

Clock Synchronizer

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

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