SSL4101T

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 1 — 21 April 2011

10 of 29

NXP Semiconductors

SSL4101T

GreenChip III+ SMPS control IC

7.2.6 Low power mode

When the output power of the flyback converter (see Section 7.3) is low, the flyback

converter switches over to frequency reduction mode. When frequency reduction mode is

entered by the flyback controller, the power factor correction circuit is switched off to

maintain high efficiency.

During low power mode operation the PFCCOMP pin is clamped to a minimal voltage of

2.7 V (typical) and a maximum voltage of 3.9 V (typical). The lower clamp voltage limits

the maximum power that is delivered when the PFC is switched on again. The upper

clamp voltage ensures that the PFC can return to its normal regulation point in a limited

amount of time when returning from low power mode.

As soon as the flyback converter leaves the frequency reduction mode, the power factor

correction circuit restores normal operation. To prevent continuous switching on and off of

the PFC circuit, a small hysteresis is build in, (60 mV (typical) on the FBCTRL pin).

7.2.7 Overcurrent protection (PFCSENSE pin)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an

measured via the PFCSENSE pin.

7.2.8 Mains undervoltage lockout/brownout protection (VINSENSE pin)

To prevent the PFC from operating at very low mains input voltages, the voltage on the

VINSENSE pin is sensed continuously. As soon as the voltage on this pin drops below the

The voltage on pin VINSENSE is clamped to a minimum value,

restored after a mains dropout.

Fig 5.

Soft start-up of PFC

SOFT START

CONTROL

OCP

11

PFCSENSE

0.5 V

Istartup(soft)PFC ≤ 60 μA

S1

RSS1

CSS1

RSENSE1

014aaa157