 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
R5F364AMDFB 数据表(PDF) 65 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F364AMDFB 数据表(HTML) 65 Page - Renesas Technology Corp |
|
|
65 / 92 page  R01DS0032EJ0200 Rev.2.00 Page 65 of 88 Feb 07, 2011 M16C/64A Group 5. Electrical Characteristics Figure 5.15 Timing Diagram BCLK CSi ADi ALE RD 25ns(max.) 0ns(min.) Hi-Z DBi 0ns(min.) BHE Read timing Memory Expansion Mode and Microprocessor Mode (in no wait state setting) 25ns(max.) 0ns(min.) BCLK CSi ADi ALE BHE 40ns(max.) 0ns(min.) DBi Write timing Hi-Z 1 V = V = 5V CC1 CC2 15ns(max.) th(BCLK-CS) tcyc th(BCLK-AD) 0ns(min.) td(BCLK-AD) td(BCLK-ALE) -4ns(min.) th(RD-AD) 0ns(min.) td(BCLK-RD) th(BCLK-RD) 0ns(min.) tac1(RD-DB) tsu(DB-RD) th(RD-DB) th(BCLK-ALE) 25ns(max.) td(BCLK-CS) 25ns(max.) td(BCLK-CS) 25ns(max.) 0ns(min.) th(BCLK-CS) tcyc 25ns(max.) 0ns(min.) 15ns(max.) td(BCLK-ALE) -4ns(min.) th(BCLK-ALE) td(BCLK-AD) th(BCLK-AD) th(WR-AD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) t = cyc Measuring conditions V = V = 5V CC1 CC2 Input timing voltage: V = 0.8 V, V = 2.0 V IL IH Output timing voltage: V = 0.4 V, V = 2.4 V OL OH f(BCLK) 40ns(min.) (0.5 × t - 40)ns(min.) cyc (0.5 × t - 10)ns(min.) cyc (0.5 × t - 10)ns(min.) cyc (0.5 × t - 45)ns(max.) cyc WR, WRL, WRH |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
