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M24LR64-R 数据表(PDF) 49 Page - STMicroelectronics |
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M24LR64-R 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 128 page  M24LR64-R Bit representation and coding Doc ID 15170 Rev 10 49/128 11.1.2 Low data rate A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of 75.52 µs as shown in Figure 27. Figure 27. Logic 0, low data rate For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of 37.76 µs as shown in Figure 28. Figure 28. Logic 0, low data rate x2 A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz (fC/32) as shown in Figure 29. Figure 29. Logic 1, low data rate For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by 16 pulses at 423.75 kHz (fC/32) as shown in Figure 29. Figure 30. Logic 1, low data rate x2 151.04µs ai12068 75.52µs ai12069 151.04µs ai12070 75.52µs ai12071 |
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