© 2011 Microchip Technology Inc.

DS40151E-page 5

HCS512

3.0

DESCRIPTION OF FUNCTIONS

3.1

Parallel Interface

The HCS512 activates the S3, S2, S1 & S0 outputs

when a new valid code is received. The outputs will be

activated for approximately 500 ms. If a repeated code

is received during this time, the output extends for

approximately 500 ms.

3.2

Serial Interface

The decoder has a PWM/Synchronous interface con-

nection to microcontrollers with limited I/O. An output

data stream is generated when a valid transmission is

received. The data stream consists of one START bit,

four function bits, one bit for battery status, one bit to

indicate a repeated transmission, two status bits, and

one STOP bit. (Table 3-1). The DATA and CLK lines are

used to send a synchronous event message.

A special status message is transmitted on the second

pass of learn. This allows the controlling microcon-

troller to determine if the learn was successful (Result

= 1) and if a previous transmitter was overwritten

(Overwrite = 1). The status message is shown in

Figure 3-2.

Table 3-1 show the values for TX1:0 and the number of

transmitters learned.

TABLE 3-1:

STATUS BITS

FIGURE 3-1:

DATA OUTPUT FORMAT

FIGURE 3-2:

STATUS MESSAGE FORMAT

A 1-wire PWM or 2-wire synchronous interface can be used.

In 1-wire mode, the data is transmitted as a PWM signal with a basic pulse width of 400

μs.

In 2-wire mode, Synchronous mode PWM bits start on the rising edge of the clock, and the bits must be sampled on the

falling edge. The START bit is a ‘1’ and the STOP bit is ‘0’.

FIGURE 3-2:

Note:

The Decoder output PWM format logic (“1” / “0”) is reversed with respect of the Encoder modulation format.

TX1

TX0

Number of Transmitters

00

One

01

Two

10

Three

1

1

Four

START

S3

S2

S1

S0

TX1

TX0

STOP

REPEAT

START

0

0

0

0

RESULT

TX1

TX0

STOP

OVRWR

S3

START

S2

S1

S0

RPT

Reserved Reserved STOP

1200

μs

CLK

DATA

LOGIC “1”

LOGIC “0”

600

μs

1200

μs

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