HCS365 datasheet(16/40 Pages) MICROCHIP

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HCS365

DS41109E-page 16

5.0

SPECIAL FEATURES

5.1

Internal RC Oscillator

The HCS365 has an onboard RC oscillator that con-

trols all the logic output timing characteristics. The

oscillator frequency varies over temperature and volt-

age variances, but stays within ±10% of the tuned

value. All the timing values specified in this document

are subject to this oscillator variation.

5.2

RF Enable and PLL Interface

The S3/SHIFT/RFEN pin of the HCS365 can be config-

ured to function as a RF enable output signal. This is

done with the RF Enable Output (RFENO) configura-

tion option. When enabled, this pin will be driven high

whenever data is transmitted through the DATA pin. If

the RFEN output is enabled it will not be possible to uti-

lize the dual encoder functionality.

In addition, the RF Enable and DATA output interfaces

with RF PLL’s. The PLL interface select (PLLSEL) con-

figuration option selects between the ASK and FSK

interfaces. Figure 5-1 shows the startup sequence for

both ASK and FSK interface options. The RFEN signal

will go low at the end of the last code word, including

the guard time.

If RFENO = 1, the RFEN pin will be driven high when-

ever data is transmitted through the DATA pin.

FIGURE 5-1:

ASK/FSK INTERFACE

5.3

LED Output

The LED pin will be driven low while the HCS365 is

transmitting data. The LED On Time (TLEDON) can be

selected between 50 ms and 100 ms with the LED On

Time Select (LEDOS) configuration option. The LED

Off Time (TLEDOFF) is fixed at 500 ms. When the VDD

voltage drops below the selected VLOW trip point, the

LED will not blink unless the LED Blink (LEDBL) option

is set. If LEDBL is set and VDD is low, then the LED will

only flash once. Waveforms of the LED behavior are

shown in Figure 5-2.

For circuits with VDD greater than 3 volts, be sure to

limit the LED circuit with a series resistor. The LED out-

put can safely sink up to 25 mA but adding an external

resistor will conserve battery power. This is an open

drain output but it does have a weak pull-up capable of

driving a CMOS input.

ASK RFEN

ASK DATA

FSK RFEN

FSK DATA

TPU

TPLL

CODE WORD

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