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HCS365 数据表(PDF) 17 Page - Microchip Technology

部件名 HCS365
功能描述  KEELOQ짰 Code Hopping Encoder Crypt keys are read protected
PDF  40 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

HCS365 数据表(HTML) 17 Page - Microchip Technology

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© 2011 Microchip Technology Inc.
DS41109E-page 17
HCS365
FIGURE 5-2:
LED OPERATION
5.4
Cyclic Redundancy Check (CRC)
The CRC bits are calculated on the 65 previously trans-
mitted bits. These bits contain the 32-bit hopping code,
32-bit fixed code, and VLOW bit. The decoder can use
the CRC bits to check the data integrity before process-
ing starts. The CRC can detect all single bit errors and
66% of double bit errors. The CRC is computed as fol-
lows:
EQUATION 5-1:
CRC Calculation
and
with
and Di
n the nth transmission bit 0 <= n <= 64
5.5
Button Queue Information
(QUEUE)
The queuing or repeated pressing of the same buttons
can be handled in two ways on the HCS365. This is
controlled with the Queue Counter Enable (QUEN)
configuration option. This option can be different for
Encoder 1 and Encoder 2.
When the QUEN option is disabled, the device will reg-
ister up to two sequential button presses. In this case,
the device will complete the minimum code words
selected with the MTX option before the second code
word is calculated and transmitted. The code word will
be 67 bits in this case, with no additional queue bits
transmitted.
If the QUEN option is enabled, the queue bits are
added to the standard code word. The queue bits are a
2-bit counter that does not wrap. The counter value
starts at 00
2 and is incremented if a button is pushed
within 2 seconds from the start of the previous button
press. The current code word is terminated when a but-
ton is queued. This allows additional functionality for
double or triple button presses.
FIGURE 5-3:
CODE WORD COMPLETION
WITH QUEN SETTINGS
6.0
PROGRAMMING
SPECIFICATIONS
Refer to the “HCS365 Programming Specifications”
document (DS41157) in Microchip Literature.
SN
LED
LED
VDD > VLOW
VDD < VLOW
TLEDON
TLEDOFF
LEDBL=1
LED
VDD < VLOW
LEDBL=0
CRC 1
[]n1
+
CRC 0
[]n Din
=
CRC 0
[]n1
+
CRC 0
[]n Din
()
CRC 1
[]n
=
CRC 1 0
,
[]0
0
=
SN
QUEN = Disabled
QUEN = Enabled
DATA
WAKE-UP
CODE2
CODE2
MTX = 01
2, WAKE > 002
CODE1
CODE1
WAKE-UP
DATA
WAKE-UP
CODE1
WAKE-UP
00
CODE2 01
CODE2 01



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