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UBA2016AP 数据表(PDF) 7 Page - NXP Semiconductors

部件名 UBA2016AP
功能描述  600 V fluorescent lamp driver with PFC, linear dimming and boost function
PDF  42 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

UBA2016AP 数据表(HTML) 7 Page - NXP Semiconductors

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UBA2016A_15_15A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 20 May 2011
7 of 42
NXP Semiconductors
UBA2016A/15/15A
600 V fluorescent lamp driver
7.2.1 Regulation loop
The control loop senses the PFC output voltage via resistors R1, R2 and the feedback
input FBPFC. The frequency compensation network C1, C2 and R4 sets the response
time and stability of the loop. The voltage at pin FBPFC is regulated to Vreg(FBPFC). When
voltage on pin FBPFC is above the regulation voltage, pin COMPPFC is charged and
when voltage on pin FBPFC is lower, pin COMPPFC is discharged. Current flow through
pin COMPPFC is controlled by the PFC Operational Transconductance Amplifier (OTA)
and its transconductance gm(PFC). The voltage on pin COMPPFC controls the PFC
on-time, ton(PFC). So when the voltage at pin FBPFC is too high, ton(PFC) is reduced and
less energy is transferred. When voltage at pin FBPFC is too low, ton(PFC) is increased and
more energy is transferred.
The voltage on pin FBPFC is sampled at the rising edge of pin GPFC and held internally
during the leading edge blanking time tleb(FBPPC) before going to the OTA to prevent
disturbance of the regulation level due to transition effects when the PFC external power
switch is turned on
The maximum ton(PFC) is set when the voltage at pin COMPPFC is clamped to
Vclamp(COMPPFC) to limit the dead time in recovering regulation after a regulation range
overshoot. The ton(PFC) time can be regulated down to zero. The moment at which the
gate is turned on is determined by pin AUXPFC. When this pin is below demagnetization
detection voltage Vdet(demag)AUXPFC and the low PFC off-time toff(PFC)low timer is finished,
the next cycle starts.
During start-up, the capacitor connected to pin COMPPFC is connected by an internal
switch to pin FBPFC which allows it to partially charge before the PFC starts. This reduces
the start-up time.
Fig 6.
Basic PFC application diagram
GND
VDD
FBPFC
GPFC
AUXPFC
COMPPFC
Vo(PFC)
VDSRmains
li(PFC)
lo(PFC)
DPFC
LPFC
mains
QPFC
Iswitch(PFC)
Dbypass
CBUS
R1
R2
R4
C2
C1
R3
001aam533
UBA2016A
UBA2015
UBA2015A



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