AD8429

Rev. 0 | Page 15 of 20

THEORY OF OPERATION

A3

A1

A2

Q2

Q1

C1

C2

+IN

–IN

R3

5kΩ

R4

5kΩ

R5

5kΩ

RG–

REF

NODE 1

NODE 2

COMPENSATION

COMPENSATION

II

R6

5kΩ

RG+

R2

3kΩ

R1

3kΩ

Figure 46. Simplified Schematic

ARCHITECTURE

The AD8429 is based on the classic 3-op

-amp topology. This

topology has two stages: a preamplifier to provide differential

amplification followed by a difference amplifier that removes

the common-mode voltage and provides additional amplifica-

tion. Figure 46 shows a simplified schematic of the AD8429.

The first stage works as follows. To keep its two inputs matched,

Amplifier A1 must keep the collector of Q1 at a constant voltage.

It does this by forcing RG− to be a precise diode drop from –IN.

Similarly, A2 forces RG+ to be a constant diode drop from +IN.

Therefore, a replica of the differential input voltage is placed

this resistance must also flow through the R1 and R2 resistors,

creating a gained differential signal between the A2 and A1

outputs.

The second stage is a G = 1 difference amplifier, composed of

Amplifier A3 and the R3 through R6 resistors. This stage removes

the common-mode signal from the amplified differential signal.

The transfer function of the AD8429 is

where:

G

R

G

kΩ

6

1+

=

GAIN SELECTION

AD8429, which can be calculated by referring to Table 5 or by

using the following gain equation:

1

kΩ

6

−

=

G

R

G

Table 5. Gains Achieved Using 1% Resistors

Calculated Gain

6.04 kΩ

1.993

1.5 kΩ

5.000

665 Ω

10.02

316 Ω

19.99

121 Ω

50.59

60.4 Ω

100.3

30.1 Ω

200.3

12.1 Ω

496.9

6.04 Ω

994.4

3.01 Ω

1994

The AD8429 defaults to G = 1 when no gain resistor is used.

specifications of the AD8429 to determine the total gain accu-

racy of the system. When the gain resistor is not used, gain

error and gain drift are minimal.

The AD8429 duplicates the differential voltage across its inputs

handle the expected power dissipation.

REFERENCE TERMINAL

The output voltage of the AD8429 is developed with respect to

the potential on the reference terminal. This is useful when the

output signal must be offset to a precise midsupply level. For

example, a voltage source can be tied to the REF pin to level

shift the output, allowing the AD8429 to drive a single-supply

ADC. The REF pin is protected with ESD diodes and should