DAC8563SDGST datasheet(7/56 Pages) TI1

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SCLK

SYNC

DIN

VOUT

DB23

DB0

LDAC

(1)

LDAC

(2)

CLR

DAC8562, DAC8563

DAC8162, DAC8163

DAC7562, DAC7563

www.ti.com

SLAS719C

– AUGUST 2010 – REVISED JUNE 2011

TIMING DIAGRAM

(1)

Asynchronous LDAC update mode. For more information, see the LDAC Functionality section.

(2)

Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.

Figure 1. Serial Write Operation

TIMING REQUIREMENTS

(1) (2)

At AVDD = 2.7 V to 5.5 V and over –40°C to 125°C (unless otherwise noted).

DAC756x/DAC816x/DAC856x

PARAMETER

UNIT

MIN

TYP

MAX

SCLK falling edge to SYNC falling edge (for successful write operation)

(3)

SCLK cycle time

SYNC rising edge to 23rd SCLK falling edge (for successful SYNC interrupt)

Minimum SYNC HIGH time

SYNC to SCLK falling edge setup time

SCLK LOW time

SCLK HIGH time

SCLK falling edge to SYNC rising edge

Data setup time

t10

Data hold time

t11

SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode

t12

LDAC pulse duration, LOW time

t13

CLR pulse duration, LOW time

t14

CLR falling edge to start of VOUT transition

100

(1)

All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VINL + VINH)/2.

(2)

See the Serial Write Operation timing diagram (Figure 1).

(3)

Maximum SCLK frequency is 50 MHz at AVDD = 2.7 V to 5.5 V.

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Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563

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