ACS411CS datasheet(22/43 Pages) SEMTECH

22 / 43 page

ACS411CS PRE-RELEASE Issue 6.0 July 1999.

Address

Bit

Access

Name

Description

0x00

7-0

id<7:0>

Device identification number.

0x01

7-0

R/W

ch_enb<8:1>

Channel enable (active low) for channels 1 to 8.

0x02

7-0

R/W

ch_enb<16:9> Channel enable (active low) for channels 9 to 16.

0x03

7-0

R/W

cm1<8:1>

Configuration mode CM bit 1 for channels 1 to 8.

0x04

7-0

R/W

cm1<16:9>

Configuration mode CM bit 1 for channels 9 to 16.

0x05

7-0

R/W

cm2<8:1>

Configuration mode CM bit 2 for channels 1 to 8.

0x06

7-0

R/W

cm2<16:9>

Configuration mode CM bit 2 for channels 9 to 16.

0x07

7-0

R/W

cm3<8:1>

Configuration mode CM bit 3 for channels 1 to 8.

0x08

7-0

R/W

cm3<16:9>

Configuration mode CM bit 3 for channels 9 to 16.

0x09

7-0

R/W

pol1<8:1>

Line code polarity POL bit 1 for channels 1 to 8.

0x0A

7-0

R/W

pol1<16:9>

Line code polarity POL bit 1 for channels 9 to 16.

0x0B

7-0

R/W

pol2<8:1>

Line code polarity POL bit 2 for channels 1 to 8.

0x0C

7-0

R/W

pol2<16:9>

Line code polarity POL bit 2 for channels 9 to 16.

0x0D

7-0

R/W

pol3<8:1>

Line code polarity POL bit 3 for channels 1 to 8.

0x0E

7-0

R/W

pol3<16:9>

Line code polarity POL bit 3 for channels 9 to 16.

0x0F

7-0

R/W

ckc<8:1>

Clock direction select for channels 1 to 8.

0x10

7-0

R/W

ckc<16:9>

Clock direction select for channels 9 to 16.

0x11

7-0

R/W

trsel<8:1>

Transmit clock edge select for channels 1 to 8.

0x12

7-0

R/W

trsel<16:9>

Transmit clock edge select for channels 9 to 16.

0x13

7-0

R/W

resel<8:1>

Receive clock edge select for channels 1 to 8.

0x14

7-0

R/W

resel<16:9>

Receive clock edge select for channels 9 to 16.

0x15

6-4

R/W

cm_m<3:1>

Configuration mode CM for maintenance channel.

R/W

CKLOCAL

Local Tx/Rx CLK setup in remote control mode

R/W

CKM

Clock direction select maintenance channel.

R/W

trsel_m

Transmit clock edge select for maintenance channel.

R/W

resel_m

Receive clock edge select for maintenance channel.

0x16

6-4

R/W

MSEL<3:1>

Maintenance channel data rate select.

R/W

ENRSB

Enable remote control setup.

2-0

R/W

DR<3:1>

Data rate select.

0x17

7-0

rl_det<8:1>

Near-end remote loop-back detect channels 1 to 8.

0x18

7-0

rl_det<16:9>

Near-end remote loop-back detect channels 9 to 16.

0x19

7-0

ll_det<8:1>

Far-end local loop-back detect channels 1 to 8.

0x1A

7-0

ll_det<16:9>

Far-end local loop-back detect channels 9 to 16.

0x1B

7-2

rlm_det

Near-end remote loop-back detect for maintenance channel.

llm_det

Far-end local loop-back detect for maintenance channel.

0x1C

DCD

Data carrier detect status.

LOSS

Loss of signal status.

R/W

ERRL

Error latch.

R/W

fail_ne

Alarm indication for near-end receive fail.

R/W

fail_fe

Alarm indication for far-end receive fail.

resync_ne

Near-end device has entered re-synchronization.

resync_fe

Far-end device has entered re-synchronization.

0x1D

7-0

R/W

errc<7:0>

8-bit saturating error counter (reset by write).

0x1E

7-0

R/W

tm<7:0>

Test mode select.

0x1F

7-0

Table 15: Memory Map

Memory Map

Table 15 shows the memory map of the ACS4110. The

location names are chosen to match the corresponding

pin names. Signals not directly equivalent to pins are in

lower case.

The device identification number id<7:0> on address

0x00 is used in EPROM mode to check if an external

memory device is connected. The value to be

programmed is 0xAA.

The whole chip set-up except DR<3:1> can be

controlled individually for each channel.

The error counter errc<7:0> (address 0x1D) is an 8-bit

saturating counter for the ERRC error pulse. A write of

a 0x00 mask to this address clears the counter to 0x00.

The status signals ERRL, fail_ne, fail_fe can also be

cleared by writing a 0 to the specific bit in the address.

For example, writing a mask of 0xDF to address 0x1C

clears the ERRL signal, but leaves other status signals

unchanged.

If the microprocessor interface is enabled (UPSEL /=

0), the default start-up values of all control bits except

POL(3:1) and CKLOCAL are taken over from the pin

values as default during reset.

ACS411CS 数据表(PDF) 22 Page - Semtech Corporation

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