PCF2129A datasheet(21/69 Pages) NXP

21 / 69 page

PCF2129A_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 7 May 2010

21 of 69

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

8.7 Reset function

The PCF2129A has a Power-On Reset (POR) and a Power-On Reset Override (PORO)

function implemented.

8.7.1 Power-On Reset (POR)

The POR is active whenever the oscillator is stopped. The oscillator is also considered to

be stopped during the time between power-on and stable crystal resonance (see

Figure 10). This time may be in the range of 200 ms to 2 s depending on temperature and

supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set

logic 1).

After POR, the following mode is entered:

• 32.768 kHz CLKOUT active

• Power-On Reset Override (PORO) available to be set

• 24 hour mode is selected

• Battery switch-over is enabled

• Battery low detection is enabled

The register values after power-on are shown in Table 4.

8.7.2 Power-On Reset Override (PORO)

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and therefore speed up on-board test of the device.

Fig 10. Dependency between POR and oscillator

001aaf897

chip in reset

chip not in reset

VDD

oscillation

internal

reset

Fig 11. Power-On Reset (POR) system

001aaj324

OSCILLATOR

0 = override inactive

1 = override active

0 = clear override mode

1 = override possible

POR_OVRD

SDA/CE

SCL

RESET

OVERRIDE

CLEAR

osc stopped

0 = stopped, 1 = running

reset

PCF2129A 数据表(PDF) 21 Page - NXP Semiconductors

PCF2129A 数据表(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

数据表下载