PCF8583 datasheet(17/37 Pages) NXP

17 / 37 page

PCF8583

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Product data sheet

Rev. 06 — 6 October 2010

17 of 37

NXP Semiconductors

PCF8583

Clock and calendar with 240 x 8-bit RAM

8.2 I2C-bus protocol

8.2.1 Addressing

Before any data is transmitted on the I2C-bus, the device which must respond is

addressed first. The addressing is always carried out with the first byte transmitted after

the start procedure.

The clock and calendar acts as a slave receiver or slave transmitter. The clock signal SCL

is only an input signal but the data signal SDA is a bidirectional line.

The clock and calendar slave address is shown in Table 5. Bit A0 corresponds to

hardware address pin A0. Connecting this pin to VDD or VSS allows the device to have one

of two different addresses.

8.2.2 Clock and calendar READ or WRITE cycles

The I2C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in

Figure 18, Figure 19 and Figure 20.

Table 5.

I2C slave address byte

Slave address

Bit

MSB

LSB

R/W

Fig 18. Master transmits to slave receiver (WRITE mode)

SLAVE ADDRESS

DATA

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

R/W

auto increment

memory register address

013aaa346

n bytes

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