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PCF8583 数据表(PDF) 20 Page - NXP Semiconductors

部件名 PCF8583
功能描述  Clock and calendar with 240 x 8-bit RAM
PDF  37 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8583 数据表(HTML) 20 Page - NXP Semiconductors

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PCF8583
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 6 October 2010
20 of 37
NXP Semiconductors
PCF8583
Clock and calendar with 240 x 8-bit RAM
10. Characteristics
10.1 Static characteristics
[1]
Typical values measured at Tamb = 25 °C.
[2]
When the device is powered on, VDD must exceed 1.5 V until the stable operation of the oscillator is established.
[3]
Event counter mode: supply current dependant upon input frequency.
[4]
See Figure 21.
[5]
The I2C-bus logic is disabled if VDD < Ven.
[6]
When the voltages are above or below the supply voltages VDD or VSS, an input current will flow; this current must not exceed ±0.5 mA.
[7]
Tested on a sample basis.
Table 7.
Static characteristics
VDD = 2.5 V to 6.0 V; VSS = 0 V; Tamb = −40 °C to +85 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VDD
supply voltage
operating mode
I2C-bus active
2.5
-
6.0
V
I2C-bus inactive
1.0
-
6.0
V
quartz oscillator
Tamb = 0 °C to +70 °C
[2]
1.0
-
6.0
V
IDD
supply current
operating mode
fSCL = 100 kHz clock mode
[3]
-
-
200
μA
clock mode; fSCL = 0 Hz
VDD = 5.0 V
[4]
-10
50
μA
VDD = 1.0 V
[4]
-2
10
μA
data retention;
fOSCI = 0 Hz; VDD = 1.0 V
Tamb = −40 °C to +85 °C
--5
μA
Tamb = −25 °C to +70 °C
--2
μA
Ven
enable voltage
I2C-bus enable level
[5]
1.5
1.9
2.3
V
Pin SDA
VIL
LOW-level input voltage
[6]
−0.8
-
0.3VDD
V
VIH
HIGH-level input voltage
[6]
0.7VDD
-VDD + 0.8 V
IOL
LOW-level output current
3.0
-
-
mA
ILI
input leakage current
−1-
+1
μA
CI
input capacitance
[7]
--7
pF
Pins A0 and OSCI
ILI
input leakage current
VI = VDD or VSS
−250
-
+250
nA
Pin INT
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
ILI
input leakage current
VI = VDD or VSS
−1-
+1
μA
Pin SCL
ILI
input leakage current
VI = VDD or VSS
−1-
+1
μA
CI
input capacitance
[7]
--7
pF



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