 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CC2500-RTY1 数据表(PDF) 22 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
CC2500-RTY1 数据表(HTML) 22 Page - Texas Instruments |
|
|
22 / 96 page  CC2500 SWRS040C Page 22 of 89 Figure 7: Configuration Register Write and Read Operations Parameter Description Min Max Units SCLK frequency 100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access). - 10 MHz SCLK frequency, single access No delay between address and data byte 9 MHz fSCLK SCLK frequency, burst access No delay between address and data byte, or between data bytes 6.5 MHz tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 µs tsp CSn low to positive edge on SCLK, in active mode 20 - ns tch Clock high 50 - ns tcl Clock low 50 - ns trise Clock rise time - 5 ns tfall Clock fall time - 5 ns Single access 55 - ns tsd Setup data (negative SCLK edge) to positive edge on SCLK (tsd applies between address and data bytes, and between data bytes) Burst access 76 - ns thd Hold data after positive edge on SCLK 20 - ns tns Negative edge on SCLK to CSn high 20 - ns Table 16: SPI Interface Timing Requirements Note: The minimum tsp,pd figure in Table 16 can be used in cases where the user does not read the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator start-up time measured on CC2500EM reference design ([4]) using crystal AT-41CD2 from NDK. 10.1 Chip Status Byte When the header byte, data byte or, command strobe is sent on the SPI interface, the chip status byte is sent by the CC2500 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running. Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
