TMP103CYFFT datasheet(12/23 Pages) TI

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SCL

SDA

(LOW)

(HDSTA)

(HDDAT)

(BUF)

(SUDAT)

(HIGH)

(SUSTA)

(SUSTO)

TMP103

SBOS545A

– FEBRUARY 2011 – REVISED MARCH 2011

www.ti.com

TIMING DIAGRAMS

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not

The TMP103 is two-wire and SMBus compatible.

limited and is determined by the master device.

Figure

describe

the

various

operations on the TMP103. Parameters for Figure 11

Acknowledge:

Each

receiving

device,

when

are defined in Table 10. Bus definitions are:

addressed, is obliged to generate an Acknowledge

bit. A device that acknowledges must pull down the

Bus Idle: Both SDA and SCL lines remain high.

SDA line during the Acknowledge clock pulse in such

a way that the SDA line is stable low during the high

Start Data Transfer: A change in the state of the

period of the Acknowledge clock pulse. Setup and

SDA line, from high to low, while the SCL line is high,

hold times must be taken into account. On a master

defines a START condition. Each data transfer is

receive, the termination of the data transfer can be

initiated with a START condition.

signaled

the

master

generating

Stop Data Transfer: A change in the state of the

Not-Acknowledge ('1') on the last byte that has been

SDA line from low to high while the SCL line is high

transmitted by the slave.

defines a STOP condition. Each data transfer is

terminated

with

repeated

START

STOP

condition.

NOTE: P = STOP, S = START.

Figure 11. Two-Wire Timing Diagram

Table 10. Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

f(SCL)

SCL Operating Frequency, VS > 1.7V

0.001

0.4

0.001

3.4

MHz

f(SCL)

SCL Operating Frequency, VS < 1.7V

0.001

0.4

0.001

2.75

MHz

t(BUF)

Bus Free Time Between STOP and START Condition

600

160

Hold time after repeated START condition.

t(HDSTA)

100

After this period, the first clock is generated.

t(SUSTA)

Repeated START Condition Setup Time

100

t(SUSTO)

STOP Condition Setup Time

100

t(HDDAT)

Data Hold Time

t(SUDAT)

Data Setup Time

100

t(LOW)

SCL Clock Low Period, VS > 1.7V

1300

160

t(LOW)

SCL Clock Low Period, VS < 1.7V

1300

200

t(HIGH)

SCL Clock High Period

600

Clock/Data Fall Time

300

Clock/Data Rise Time

300

160

Clock/Data Rise Time for SCLK

≤ 100kHz

1000

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