Description

STV7623

4/27

Doc ID 018939 Rev 1

1.1

Pin description

Figure 2.

PCB-Less COF pinout diagram

Figure 2 shows the possible design of a custom COF with wire on array (WOA) routing

(PCB-less). This example supports only 480 outputs.

Table 2.

Pin description

Pin name

I/O

Function

Description

CLK

In

Shift clock Input

Clock input for the chip internal shift register. Data

is shifted at each rising edge of this clock.

DIR

In

Shift direction

Control pin

This pin controls the output shifting direction.

STV1

STV2

I/O

Start pulse

input/output pin

These pins are used to control the channel start

pulse input or output pin. The function of these

two pins depends on the status of DIR pin (refer

to the Section 3: Truth tables)

BLANK

In

Output enable

control

This pin is used to control the channel output.

When BLANK is high, the shift register is

bypassed (overriden) and all driver outputs are

fixed to VN level instantly, (when POL= L).

It is assumed this signal affect few outputs

O U T480

VP

DVD D

DG N D

VN

ST V 2

T EST

DIR

CL K

BL ANK

PO L

BL ANK

CL K

DIR

LE N G TH

ST V 1

VN

DG N D

DVD D

VP

0U T 1

Te s t1 0

Te s t9

Te s t8

Te s t7

Te s t6

Te s t5

Te s t4

Te s t3

Te s t2

Te s t1

Te s t2 0

Te s t1 9

Te s t1 8

Te s t1 7

Te s t1 6

Te s t1 5

Te s t1 4

Te s t1 3

Te s t1 2

Te s t1 1

Te st1 0

Test9

Test8

Test7

Test6

Test5

Test4

Test3

Test2

Test1

Te st1 0

Test9

Test8

Test7

Test6

Test5

Test4

Test3

Test2

Test1

Te st2 0

Te st1 9

Te st1 8

Te st1 7

Te st1 6

Te st1 5

Te st1 4

Te st1 3

Te st1 2

Te st1 1

Te st2 0

Te st1 9

Te st1 8

Te st1 7

Te st1 6

Te st1 5

Te st1 4

Te st1 3

Te st1 2

Te st1 1

O U T 480

VP

DV DD

DGND

VN

STV 2

T EST

BL ANK

PO L

BL ANK

CL K

DIR

LE N G T H

STV 1

VN

DGND

DV DD

VP

0U T 1

DV DD

PO L

DIR

CL K

DGND

JU S T IF Y

Test2 0

Test1 9

Test1 8

Test1 7

Test1 6

Test1 5

Test1 4

Test1 3

Test1 2

Test1 1

Test2 0

Test1 9

Test1 8

Test1 7

Test1 6

Test1 5

Test1 4

Test1 3

Test1 2

Test1 1

O u t480

O u t479

O u t478

O u t477

-

-

-

-

-

-

O u t480

O u t479

O u t478

O u t477

-

-

-

-

-

-

Test1 0

Test9

Test8

Test7

Test6

Test5

Test4

Test3

Test2

Test1

Test1 0

Test9

Test8

Test7

Test6

Test5

Test4

Test3

Test2

Test1

-

-

-

-

-

-

Ou t4

Ou t3

Ou t2

Ou t1

-

-

-

-

-

-

Ou t4

Ou t3

Ou t2

Ou t1