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STV7623 数据表(PDF) 5 Page - STMicroelectronics |
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STV7623 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 27 page ![]() STV7623 Description Doc ID 018939 Rev 1 5/27 In the pinout diagram: ● TEST is used to test the device. POL In Polarity pin When POL is low, VP and VN are swapped functionally at the output pins level. This signal is assumed static. OUT1..OUT480 Out Driver output pins The output voltage is either VP or VN for driving the gate electrode, depending on the data stored in the shift register. It is assumed that only up to 4 outputs are changing level simultaneously. VP Power Power supply High voltage supply (eg +50 V) DVDD Power Power supply Digital power supply DGND Power Power supply Digital ground VN Power Power supply Negative supply TEST In Test pin Test pin (must be grounded in application) LENGTH In Nb of active outputs When LENGTH =0, enable 480 outputs When LENGTH =1, enable 400 outputs This signal is assumed static JUSTIFY In Partial output justify mode Only applicable when LENGTH=1 When JUSTIFY = 0, use outputs 0 to 399 When JUSTIFY = 1, use outputs 80 to 479 This signal is assumed static. Table 2. Pin description (continued) Pin name I/O Function Description |
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