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AS8221-ASSP 数据表(PDF) 24 Page - ams AG |
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AS8221-ASSP 数据表(HTML) 24 Page - ams AG |
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24 / 41 page ![]() AS8221 Datasheet - Application In form atio n www.austriamicrosystems.com/flexray/AS8221 Revision 1.4 24 - 41 9.6.1 Error and Status Flag Bit Order When the read-out mechanism is started, the first data information is the Bit 0 until Bit 15 is transmitted. Any re-initiation or repetitions is started with the first data Bit 0. 9.7 Bus Driver 9.7.1 Bus States Activity: The bus wires reflects the differential signal specified in chapter 9.9 Transmitter on page 26. Idle: The bus wires are terminated to VCC/2 via. receiver input resistances. Idle_LP: The bus wires are terminated to GND via receiver input resistances. Idle_HZ: The bus wires are not terminated to VCC/2 via. 1M Ω Table 10. Bit Order for the Read-out Sequence Bit Description Symbol Bit 0 Undervoltage VBAT detected UVVBAT_DET Bit 1 Undervoltage VIO detected UVVIO_DET Bit 2 Undervoltage VCC detected UVVCC_DET Bit 3 Bus error BUSERR Bit 4 Reserved Reserved Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Short circuit between BP and BM BP_BM Bit 11 Over temperature OT Bit 12 TxEN_BGE timeout TxEN_TO Bit 13 Local wake flag LWAKE Bit 14 Remote wake flag RWAKE Bit 15 Power on flag PWON |
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