ADP150

Rev. A | Page 18 of 20

OUTLINE DIMENSIONS

*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

1.60 BSC

2.80 BSC

1.90

BSC

0.95 BSC

0.20

0.08

0.60

0.45

0.30

8°

4°

0°

0.50

0.30

0.10 MAX

*1.00 MAX

*0.90 MAX

0.70 MIN

2.90 BSC

5

4

1

2

3

SEATING

PLANE

Figure 49. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions show in millimeters

0.050 NOM

COPLANARITY

0.800

0.760 SQ

0.720

0.230

0.200

0.170

0.280

0.260

0.240

0.660

0.600

0.540

0.430

0.400

0.370

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

A

1

2

B

SEATING

PLANE

0.40

BALL PITCH

BALL A1

IDENTIFIER

Figure 50.4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-3)

Dimensions show in millimeters