DS1321 datasheet(11/12 Pages) DALLAS

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DS1321

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NOTES:

1. All voltages referenced to ground.

2. Measured with outputs open circuited.

3. ICCO1 is the maximum average load which the DS1321 can supply to attached memories at VCCO

VCCI -0.2V.

4. ICCO2 is the maximum average load which the DS1321 can supply to attached memories at VCCO

VCCI -0.3V.

5. All inputs within 0.3V of ground or VCCI.

6. ICCO3 is the maximum average load current which the DS1321 can supply to the memories in the

battery backup mode at VCCO

³ VBAT -0.2V.

7. Measured with a load as shown in Figure 1.

8. Chip Enable Outputs CEO1 - CEO4 can only sustain leakage current in the battery backup mode.

9. CEO1 through CEO4 will be held high for a time equal to tREC after VCCI crosses VCCTP on power-up.

10. BW and RST are open drain outputs and, as such, cannot source current. External pullup resistors

should be connected to these pins for proper operation. Both BW and RST can sink 10 mA.

11. tCE maximum must be met to ensure data integrity on power down.

12. In battery backup mode, inputs must never be below ground or above VCCO.

13. The DS1321 is recognized by Underwriters Laboratory (U.L.®) under file E99151.

DC TEST CONDITIONS

Outputs Open

All voltages are referenced to ground

AC TEST CONDITIONS

Output Load: See below

Input Pulse Levels: 0 - 3.0V

Timing Measurement Reference Levels

Input: 1.5V

Output: 1.5V

Input pulse Rise and Fall Times: 5 ns

OUTPUT LOAD Figure 3

*INCLUDING SCOPE AND JIG CAPACITANCE

DS1321 数据表(PDF) 11 Page - Dallas Semiconductor