DS1321 datasheet(2/12 Pages) DALLAS

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DS1321

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DESCRIPTION

The DS1321 Flexible Nonvolatile Controller with Lithium Battery Monitor is a CMOS circuit which

solves the application problem of converting CMOS SRAMs into nonvolatile memory. Incoming power

is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable outputs are

inhibited to accomplish write protection and the battery is switched on to supply the SRAMs with

uninterrupted power. Special circuitry uses a low-leakage CMOS process which affords precise voltage

detection at extremely low battery consumption. One DS1321 can support as many as four SRAMs

arranged in any of three memory configurations.

In addition to battery-backup support, the DS1321 performs the important function of monitoring the

remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life.

Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority

of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1321

performs such measurement by periodically comparing the voltage of the battery as it supports an internal

resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference

voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning

pin is activated to signal the need for battery replacement.

MEMORY BACKUP

The DS1321 performs all the circuit functions required to provide battery-backup for as many as four

SRAMs. First, the device provides a switch to direct power from the battery or the system power supply

(VCCI). Whenever VCCI is less than the VCCTP trip point and VCCI is less than the battery voltage VBAT, the

battery is switched in to provide backup power to the SRAM. This switch has voltage drop of less than

0.2 volts.

Second, the DS1321 handles power failure detection and SRAM write-protection. VCCI is constantly

monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and

inhibits the four chip enable outputs in order to write-protect the SRAMs. This is accomplished by

holding CEO1 through CEO4 to within 0.2 volts of VCCO when VCCI is out of tolerance. If any CEI is

active (low) at the time that power failure is detected, the corresponding CEO signal is kept low until the

CEI

signal is brought high again. Once the CEI signal is brought high, the CEO signal is taken high and

held high until after VCCI has returned to its nominal voltage level. If the CEI signal is not brought high

by 1.5 µs after power failure is detected, the corresponding CEO is forced high at that time. This specific

scheme for delaying write protection for up to 1.5 µs guarantees that any memory access in progress

when power failure occurs will complete properly. Power failure detection occurs in the range of 4.75 to

4.5 volts (5% tolerance) when the TOL pin is wired to GND or in the range of 4.5 to 4.25 volts (10%

tolerance) when TOL is connected to VCCO.

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