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GS9062-CF 数据表(PDF) 21 Page - Gennum Corporation

部件名 GS9062-CF
功能描述  HD-LINX II SD-SDI and DVB-ASI Serializer with ClockCleaner
PDF  46 Pages
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制造商  GENNUM [Gennum Corporation]
网页  http://www.gennum.com
标志 GENNUM - Gennum Corporation

GS9062-CF 数据表(HTML) 21 Page - Gennum Corporation

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GS9062 Data Sheet
22209 - 7
February 2007
21 of 46
3. Detailed Description
3.1 Functional Overview
The GS9062 is a dual-standard serializer with an integrated cable driver. When
used in conjunction with the external GO1555/GO1525* Voltage Controlled
Oscillator, a transmit solution at 270Mb/s is realized.
The device has three different modes of operation which must be set by the
application layer through external device pins.
When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit
demultiplexed SMPTE compliant data. The device’s additional processing features
are also enabled in this mode.
In DVB-ASI mode, the GS9062 will accept an 8-bit parallel DVB-ASI compliant
transport stream on its upper input bus. The serial output data stream will be
8b/10b encoded and stuffed.
The GS9062’s third mode allows for the serializing of data not conforming to
SMPTE or DVB-ASI streams.
The provided serial digital outputs feature a high impedance mode, output mute on
loss of parallel clock and adjustable signal swing.
In the digital signal processing core, several data processing functions are
implemented including SMPTE 352M and EDH data packet generation and
insertion, and automatic video standards detection. These features are all enabled
by default, but may be individually disabled via internal registers accessible
through the GSPI host interface.
Finally, the GS9062 contains a JTAG interface for boundary scan test
implementations.
*For new designs use GO1555
3.2 Parallel Data Inputs
Data inputs enter the device on the rising edge of PCLK as shown in Figure 3-1.
The input data format is defined by the setting of the external SMPTE_BYPASS
and DVB_ASI pins and may be presented in 10-bit or 20-bit format. The input data
bus width is controlled independently from the internal data bus width by the
20bit/10bit input pin.



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