GS9062-CF datasheet(41/46 Pages) GENNUM

41 / 46 page

GS9062 Data Sheet

22209 - 7

February 2007

41 of 46

Alternatively, if the test capabilities are to be used in the system, the host may still

control the JTAG/HOST input signal, but some means for tri-stating the host must

exist in order to use the interface at ATE. This is represented in Figure 3-12.

Figure 3-12: System JTAG

Please contact your Gennum representative to obtain the BSDL model for the

GS9062.

3.12 Device Power Up

Because the GS9062 is designed to operate in a multi-volt environment, any power

up sequence is allowed. The charge pump, phase detector, core logic, serial digital

output buffers and digital I/O buffers should all be powered up within 1ms of one

another.

Device pins may also be driven prior to power up without causing damage.

To ensure that all internal registers are cleared upon power-up, the RESET_TRST

signal must be held LOW for a minimum of 1ms after the core power supply has

reached the minimum level specified in the DC Electrical Characteristics Table.

See Table 2-1. See Figure 3-13.

3.13 Device Reset

In order to initialize all internal operating conditions to their default states the

RESET_TRST

signal must be held LOW for a minimum of t

reset = 1ms.

When held in reset, all device outputs will be driven to a high-impedance state.

Figure 3-13: Reset Pulse

Application HOST

GS9062

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

JTAG_HOST

In-circuit ATE probe

Tri-State

CORE_VDD

RESET_TRST

treset

+1.65V

+1.8V

Reset

treset

GS9062-CF 数据表(PDF) 41 Page - Gennum Corporation

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