FM3130-G datasheet(13/22 Pages) RAMTRON

13 / 22 page

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FM3130 Integrated RTC/Alarm with 64Kb FRAM

Rev. 3.2

Sept. 2011

Page 13 of 22

The FM3130 has two Slave Addresses (Slave IDs)

associated with two logical devices. To access the

memory device, bits 7-4 should be set to 1010b. The

other logical device within the FM3130 is the real-

time clock and alarm. To access this device, bits 7-4

of the slave address should be set to 1101b. A bus

transaction with this slave address will not affect the

memory in any way. The figures below illustrate the

two Slave Addresses.

Bits 3 through 1 of the Slave Address must be logic

0. Bit 0 is the read/write bit. A „1‟ indicates a read

operation, and a „0‟ indicates a write operation.

Figure 5. Slave Address – Memory

Figure 6. Slave Address – RTC

Addressing Overview – Memory

After the FM3130 acknowledges the Slave Address,

the master can place the memory address on the bus

for a write operation. The address requires two bytes.

The first is the MSB (upper byte). The first 3 unused

address bits are don‟t cares, but should be set to „0‟

to maintain upward compatibility. Following the

MSB is the LSB (lower byte) which contains the

remaining eight address bits. The address is latched

internally. Each access causes the latched address to

be incremented automatically. The current address is

the value that is held in the latch, either a newly

written value or the address following the last access.

The current address will be held as long as VDD is

greater than VSW or until a new value is written.

Accesses to the clock do not affect the current

memory address. Reads always use the current

address. A random read address can be loaded by

beginning a write operation as explained below.

After transmission of each data byte, just prior to the

Acknowledge, the FM3130 increments the internal

address. This allows the next sequential byte to be

accessed with no additional addressing externally.

After the last address is reached, the address latch

will roll over to 0000h. There is no limit to the

number of bytes that can be accessed with a single

read or write operation.

Addressing Overview – RTC/Alarm

The RTC/Alarm operates in a similar manner to the

memory, except that it uses only one byte of address.

Addresses 00h to 0Eh correspond to the RTC/Alarm

and control registers. Attempting to load addresses

above 0Eh is an illegal condition; the FM3130 will

return a NACK and abort the 2-wire transaction.

Data Transfer

After the address information has been transmitted,

data transfer between the bus master and the

FM3130 begins. For a read, the FM3130 will place 8

data bits on the bus then wait for an ACK from the

master. If the ACK occurs, the FM3130 will transfer

the next byte. If the ACK is not sent, the FM3130

will end the read operation. For a write operation, the

FM3130 will accept 8 data bits from the master then

send an Acknowledge. All data transfer occurs MSB

(most significant bit) first.

Memory Write Operation

All memory writes begin with a Slave Address, then

a memory address. The bus master indicates a write

operation by setting the slave address LSB to a „0‟.

After addressing, the bus master sends each byte of

data to the memory and the memory generates an

Acknowledge condition. Any number of sequential

bytes may be written. If the end of the address range

is reached internally, the address counter will wrap

to 0000h. Internally, the actual memory write occurs

after the 8

th data bit is transferred. It will be complete

before the Acknowledge is sent. Therefore, if the

user desires to abort a write without altering the

memory contents, this should be done using a Start

or Stop condition prior to the 8

th data bit. The figures

below illustrate a single- and multiple-writes to

memory.

R/W

Slave ID

R/W

Slave ID

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