PFS704 datasheet(18/30 Pages) POWERINT

18 / 30 page

Rev. D 12/11

PFS704-729EG

www.powerint.com

To minimize effect of trace impedance affecting regulation,

output feedback should be taken directly from the output

capacitor positive terminal. The upper end of the line-sense

resistors should be connected to the high frequency filter

capacitor connected at the output of the bridge rectifier.

Quick Design Checklist

As with any power supply design, all HiperPFS designs should

be verified on the bench to make sure that component

specifications are not exceeded under worst-case conditions.

The following minimum set of tests is strongly recommended:

1. Maximum drain voltage – verify that peak V

DS does not

exceed 530 V at lowest input voltage and maximum overload

output power. Maximum overload output power occurs

when the output is overloaded to a level just above the

highest rated load or before the power supply output voltage

starts falling out of regulation. Additional external snubbers

should be used if this voltage is exceeded. In most designs,

addition of a ceramic capacitor in the range of 33 pF and

100 pF connected across the PFC output diode will reduce

the maximum drain-source voltage to a level below the BV

DSS

rating. When measuring drain-source voltage of the MOSFET,

a high voltage probe should be used. When the probe tip is

removed, a silver ring in the vicinity of the probe tip can be

seen. This ring is at ground potential and the best ground

connection point for making noise free measurements.

Wrapping stiff wire around the ground ring and then

connecting that ground wire into the circuit with the shortest

possible wire length, and connecting the probe tip to the

point being measured, ensures error free measurement.

2. Maximum drain current – at maximum ambient temperature,

minimum input voltage and maximum output load, verify

drain current waveforms at start-up for any signs of inductor

saturation and excessive leading edge current spikes.

HiperPFS has a leading edge blanking time of 220 ns to

prevent premature termination of the ON-cycle. Verify that

the leading edge current spike is below the allowed current

limit for the drain current waveform at the end of the 220 ns

blanking period. If a wire loop is inserted in series with the

drain, it forms a small stray inductance in series with the

drain. This stray inductance will add to the leading edge

voltage spike on the drain source waveform. The drain-

source voltage waveform should therefore never be measured

with this loop. An alternate measurement that can provide

drain current level and information regarding slope of the

inductor current can be obtained by monitoring the inductor

current instead. A wire loop can be added in series with the

PFC inductor connection that connects the inductor to the

input rectifier for the purpose of measurement.

3. Thermal check – at maximum output power, minimum input

voltage and maximum ambient temperature; verify that

temperature specifications are not exceeded for the HiperPFS,

PFC inductor, output diodes and output capacitors. Enough

thermal margin should be allowed for the part-to-part

variation of the R

DS(ON) of HiperPFS, as specified in the data

sheet. A maximum package temperature of 100 °C is

recommended to allow for these variations.

4. Input PF should improve with load, if performance is found to

progressively deteriorate with loading then that is a sign of

possible noise pickup by the VOLTAGE MONITOR pin circuit

or the feedback divider network and the compensation

circuit.

PFS704 数据表(PDF) 18 Page - Power Integrations, Inc.

PFS704 数据表(HTML) 18 Page - Power Integrations, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表下载