Register description

LIS331HH

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Doc ID 16366 Rev 1

BDU bit is used to inhibit output registers update between the reading of upper and lower

register parts. In default mode (BDU = ‘0’) the lower and upper register parts are updated

continuously. If it is not sure to read faster than output data rate, it is recommended to set

BDU bit to ‘1’. In this way, after the reading of the lower (upper) register part, the content of

that output registers is not updated until the upper (lower) part is read too.

This feature avoids reading LSB and MSB related to different samples.

7.5

CTRL_REG5 (24h)

TurnOn bits are used for turning on the sleep to wake function.

Setting TurnOn[1:0] bits to 11 the “sleep to wake” function is enabled. When an interrupt

event occurs the device is turned to normal mode increasing the ODR to the value defined in

CTRL_REG1. Although the device is in normal mode, CTRL_REG1 content is not

automatically changed to “normal mode” configuration.

7.6

HP_FILTER_RESET (25h)

Dummy register. Reading at this address zeroes instantaneously the content of the internal

high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0

g.

This allows to overcome the settling time of the high pass filter.

7.7

REFERENCE (26h)

Table 29.

CTRL_REG5 register

0

000

00

TurnOn1

TurnOn0

Table 30.

CTRL_REG5 description

TurnOn1,

TurnOn0

Turn-on mode selection for sleep to wake function. Default value: 00.

Table 31.

Sleep to wake configuration

TurnOn1

TurnOn0

Sleep to wake status

0

0

Sleep to wake function is disabled

11

Turned on: The device is in low power mode (ODR is defined in

CTRL_REG1)

Table 32.

REFERENCE register

Ref7

Ref6

Ref5

Ref4

Ref3

Ref2

Ref1

Ref0