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ADL5811ACPZ-R7 数据表(PDF) 4 Page - Analog Devices

部件名 ADL5811ACPZ-R7
功能描述  High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5811ACPZ-R7 数据表(HTML) 4 Page - Analog Devices

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ADL5811
Rev. 0 | Page 4 of 28
TIMING CHARACTERISTICS
Low logic level ≤ 0.4 V, and high logic level ≥ 1.4 V.
Table 2. Serial Interface Timing
Parameter
Limit
Unit
Test Conditions/Comments
t1
20
ns minimum
LE setup time
t2
10
ns minimum
DATA-to-CLK setup time
t3
10
ns minimum
DATA-to-CLK hold time
t4
25
ns minimum
CLK high duration
t5
25
ns minimum
CLK low duration
t6
10
ns minimum
CLK-to-LE setup time
t7
20
ns minimum
LE pulse width
Timing Diagram
CLK
DATA
LE
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t2
t3
t7
t6
t1
t4
t5
Figure 2. Timing Diagram



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