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ADL5811ACPZ-R7 数据表(PDF) 24 Page - Analog Devices

部件名 ADL5811ACPZ-R7
功能描述  High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5811ACPZ-R7 数据表(HTML) 24 Page - Analog Devices

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ADL5811
Rev. 0 | Page 24 of 28
REGISTER STRUCTURE
Figure 60 illustrates the register map of the ADL5811. The
ADL5811 only uses Register 5. Because of this, set all of the
control bits to 5. When set to 0, the ENBL bit, DB7, enables the
part. By setting this bit to 1, the mixer is powered down. The
RFB IN CAP DAC and RFB OUT CAP DAC bits are used to tune
the RF balun. In most cases, they are tuned together with the
higher settings, 7, tuning for the low frequencies, and with the
lower settings, 0, tuning for the high frequencies. There are
times where it becomes advantageous to tune the input and
output of the RF balun separately and that ability is provided.
The LPF bits control the low-pass filter settings at the IF output.
The ability to tune the low-pass filter allows some trade-off
between gain, noise figure, and input IP3 with higher settings,
7, providing higher input IP3 at the cost of some gain and noise
figure, and lower settings, 0, providing higher gain and lower
NF at the cost of lower input IP3. The VGS bits control the VGS
settings of the mixer core and allow further tuning of the device.
Table 11 lists the optimum settings characterized for each
frequency band. All register bits default to 0.
ENBL
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
VGS2 VGS1 VGS0 LPF1 LPF0
0
CDO2 DCDO1 CDO0
0
CDI2
CDI1 CDI0
0
EN
0
0
0
0
C3(1) C2(0) C1(1)
RESERVED
CONTROL BITS
VGS
LPF
RFB OUT CAP DAC
RFB IN CAP DAC
RESERVED
MEN
MAIN ENABLE
0
DEVICE ENABLED
1
DEVICE DISABLED
CDO2 CDO1 CDO0 RF BALUN OUTPUT TUNING
00
0
0
''
'
'
11
1
7
CDI2 CDI1 CDI0 RF BALUN INTPUT TUNING
00
0
0
''
'
'
11
1
7
LPF1 LPF0 LOW PASS FILTER SETTING
00
0
''
'
11
3
VGS2 VGS1 VGS0
VGS SETTING
00
0
0
''
'
'
11
1
7
Figure 60. ADL5811 Register Maps
Table 11. Optimum Settings
RF Frequency (MHz)
LO Frequency (MHz)
VGS
LPF
RFB OUT CAP DAC
RFB IN CAP DAC
700
497
3
1
7
7
800
597
1
1
6
6
900
697
2
1
6
6
1000
797
1
1
4
4
1100
897
3
1
7
7
1200
997
3
3
5
5
1300
1097
3
3
5
5
1400
1197
3
3
4
4
1500
1297
3
3
4
4
1600
1397
3
3
3
3
1700
1497
3
3
3
3
1800
1597
3
3
3
3
1900
1697
3
3
2
2
2000
1797
3
3
2
2
2100
1897
3
3
1
1
2200
1997
2
3
2
2
2300
2097
3
2
2
2
2400
2197
2
2
2
2
2500
2297
3
3
1
1
2600
2397
3
2
2
2
2700
2497
1
2
2
2
2800
2597
3
2
1
1



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