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ADL5812ACPZ-R7 数据表(PDF) 22 Page - Analog Devices

部件名 ADL5812ACPZ-R7
功能描述  Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5812ACPZ-R7 数据表(HTML) 22 Page - Analog Devices

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ADL5812
Rev. 0 | Page 22 of 28
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5812 mixer is designed to downconvert radio
frequencies (RF) primarily between 700 MHz and 2800 MHz
to lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 60 depicts the basic connections of the mixer.
It is recommended to ac couple RF and LO input ports to
prevent nonzero dc voltages from damaging the RF balun or LO
input circuit. A RFIN capacitor value of 22 pF is recommended.
IF PORT
The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.
The real part of the output impedance is approximately 200 Ω,
as seen in Figure 31, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion gain that is approximately 6 dB higher than the power
conversion gain. When a 50 Ω output impedance is needed, use a
4:1 impedance transformer, as shown in Figure 60.
BIAS RESISTOR SELECTION
External resistors, R1 and R2, are used to adjust the bias current
of the integrated amplifier at the IF terminal. It is necessary to have
a sufficient amount of current to bias both the internal IF amplifier
to optimize dc current vs. optimum input IP3 performance.
Figure 42 and Figure 43 provide the reference for the bias
resistor selection when lower power consumption is considered at
the expense of conversion gain and input IP3 performance.
VCC
RED
BLK
VPOS
AGND
C25
22pF
C24
22pF
RFIN2
C17
22pF
RFIN2
C6
22pF
RFIN1
30
29
28
27
26
25
24
23
22
21
1
PAD
VCC
VCC
VCC
VCC
C3
120pF
C4
120pF
C2
0.1µF
C13
10pF
VCC
C14
10pF
C12
10pF
C11
10pF
C5
120pF
C8
0.1µF
C7
22pF
C2.3
10pF
3
4
6
2
1
C1
0.1µF
IFON
IFOP
R20
OPEN
R21
0Ω
R1
910Ω
T1
TC4-1W+
L1
470nH
L2
470nH
VCC
VCC
VCC
VCC
VCC
C3
120pF
C4
120pF
C27
0.1µF
C20
10pF
C19
10pF
C18
10pF
C16
22pF
C15
10pF
C30
120pF
3
4
6
2
1
C26
0.1µF
IFON
IFOP
R23
OPEN
R22
0Ω
R2
910Ω
T1
TC4-1W+
L3
470nH
L4
470nH
RF1
RFCT1
NC
NC
NC
NC
NC
NC
RFCT2
RF2
V1LO1
NC
NC
NC
LOIP
LOIN
LE
DATA
CLK
LE
DATA
CLK
V2LO1
ADL5812
2
3
4
5
6
7
8
9
10
Figure 60. Evaluation Board Schematic



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