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C511 数据表(PDF) 21 Page - Siemens Semiconductor Group |
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C511 数据表(HTML) 21 Page - Siemens Semiconductor Group |
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21 / 43 page ![]() C511 / C513 Semiconductor Group 21 Timer/ Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 7: Table 7 Timer/Counter 0 and 1 operating modes In “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is f OSC/12. In “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is f OSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 7 illustrates the input clock logic. Figure 7 Timer/Counter 0 and 1 Input Clock Logic Mode Description TMOD Input Clock Gate C/T M1 M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler XX 0 0 f OSC/12 × 32 f OSC/24 × 32 1 16-bit timer/counter X X 0 1 f OSC/12 f OSC/24 2 8-bit timer/counter with 8-bit auto-reload XX 1 0 f OSC/12 f OSC/24 3 Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops XX 1 1 f OSC/12 f OSC/24 |
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