Semiconductor Group

28

C511 / C513

Table 13

Interrupt Sources and their Corresponding Interrupt Vectors

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-

priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.

If two requests of different priority level are received simultaneously, the request of higher priority is

serviced. If requests of the same priority are received simultaneously, an internal polling sequence

determines which request is serviced. Thus within each priority level there is a second priority

structure determined by the polling sequence as shown in table 14.

Source (Request Flags)

Vector

Vector Address

IE0

TF0

IE1

TF1

RI + TI

TF2 + EXF2

SSCI

External interrupt 0

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

USART serial port interrupt,

(C513/C513A/C513A-H only)

Timer 2 interrupt

Synchronous serial channel

interrupt (SSC)

0003H

000BH

0013H

001BH

0023H

002BH

0043H

Table 14

Priority-within-Level Structure

Interrupt Source

Priority

External Interrupt 0,

IE0

Synchronous Serial Channel SSC

Timer 0 Interrupt,

TF0

External Interrupt 1,

IE1

Timer 1 Interrupt,

TF1

Universal Serial Channel,

RI or TI

Timer 2 Interrupt,

TF2 or EXF2

High

↓

Low