Data Sheet

©2009-2012 CADEKA Microcircuits, LLC

www.cadeka.com

14

supply decoupling

Place the 6.8µF capacitor within 0.75 inches of the power

pin

Place the 0.1µF capacitor within 0.1 inches of the power pin

Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance

Minimize all trace lengths to reduce series inductances

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in

Figures 7-9. These evaluation boards are built for dual

supply operation. Follow these steps to use the board

in a single-supply application:

1. Short -Vs to ground.

2. Use C3 (6.8uF) and C4 (0.1uF), if the -VS pin of the

amplifier is not directly connected to the ground plane.

Figure 7. CEB004 Schematic

Figure 8. CEB004 Top View

Figure 9. CEB004 Bottom View

+

-

0.1µF

6.8µF

Output

Input

0.1µF

6.8µF

1

3

2

5

4