AD5735

Data Sheet

Rev. B | Page 12 of 48

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

REFGND

REFGND

AD0

AD1

SYNC

SCLK

SDIN

SDO

DGND

LDAC

CLEAR

ALERT

FAULT

AGND

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AD5735

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

NOTES

1.THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIAL OF THE

IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A

COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.

Figure 7. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

2

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

3

REFGND

Ground Reference Point for Internal Reference.

4

REFGND

Ground Reference Point for Internal Reference.

5

AD0

Address Decode for the Device Under Test (DUT) on the Board.

6

AD1

Address Decode for the DUT on the Board.

7

SYNC

Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked

into the input shift register on the falling edge of SCLK.

8

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface

operates at clock speeds of up to 30 MHz.

9

SDIN

Serial Data Input. Data must be valid on the falling edge of SCLK.

10

SDO

Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5).

11

Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V.

12

DGND

Digital Ground.

13

LDAC

Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs.

When LDAC is tied permanently low, the addressed DAC data register is updated on the rising edge of

SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output

is updated only on the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be

updated simultaneously. The LDAC pin must not be left unconnected.

14

CLEAR

Active High, Edge Sensitive Input. When this pin is asserted, the output current and voltage are set to the

programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information,

see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to.