Data Sheet

AD5760

Rev. B | Page 9 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

AD5760

TOP VIEW

(Not to Scale)

RESET

CLR

LDAC

SYNC

DGND

SCLK

2

1

3

4

5

6

7

18

19

17

16

15

14

13

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V

TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY

UNCONNECTED PROVIDED THAT A SUPPLY

RECOMMENDED THAT THE PADDLE BE THERMALLY

CONNECTED TO A COPPER PLANE FOR ENHANCED

THERMAL PERFORMANCE.

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Analog Output Voltage.

2

3, 5

Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin.

4

RESET

Active Low Reset. Asserting this pin returns the AD5760 to its power-on status.

6

CLR

Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates

the DAC output. The output value depends on the DAC register coding that is being used, either binary or

twos complement.

7

LDAC

Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog

output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high

during the write cycle, the input register is updated, but the output update is held off until the falling edge

of LDAC. Do not leave the LDAC pin unconnected.

8

9

Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage

range is from 1.71 V to 5.5 V.

10, 21, 22, 23

DNC

Do Not Connect. Do not connect to these pins.

11

SDO

Serial Data Output.

12

SDIN

Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling

edge of the serial clock input.

13

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates of up to 35 MHz.

14

SYNC

Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When

SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the

following clocks. The DAC is updated on the rising edge of SYNC.

15

DGND

Ground Reference Pin for Digital Circuitry.

16

Negative Reference Voltage Input.

17, 18

Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected to this

19

AGND

Ground Reference Pin for Analog Circuitry.