AD5780 datasheet(21/32 Pages) AD

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Data Sheet

AD5760

Rev. B | Page 21 of 32

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can be used

only if SYNC is held low for the correct number of clock cycles.

In gated clock mode, a burst clock containing the exact number

of clock cycles must be used, and SYNC must be taken high after

the final clock to latch the data. The first falling edge of SYNC

starts the write cycle. Exactly 24 falling clock edges must be applied

to SCLK before SYNC is brought high again. If SYNC is brought

high before the 24th falling SCLK edge, the data written is invalid.

If more than 24 falling SCLK edges are applied before SYNC is

brought high, the input data is also invalid.

The input shift register is updated on the rising edge of SYNC.

For another serial transfer to take place, SYNC must be brought

low again. After the end of the serial data transfer, data is

automatically transferred from the input shift register to the

addressed register. When the write cycle is complete, the output

can be updated by taking LDAC low while SYNC is high.

Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be

used to daisy chain several devices together. Daisy-chain mode

can be useful in system diagnostics and in reducing the number

of serial interface lines. The first falling edge of SYNC starts

the write cycle. SCLK is continuously applied to the input shift

applied, the data ripples out of the shift register and appears on

the SDO line. This data is clocked out on the rising edge of

SCLK and is valid on the falling edge. By connecting the SDO

of the first device to the SDIN input of the next device in the

chain, a multidevice interface is constructed. Each device in the

system requires 24 clock pulses. Therefore, the total number of

clock cycles must equal 24 × N, where N is the total number of

devices in the chain. When the serial transfer to all

devices is complete,

AD5760

SYNC is taken high. This latches the input

data in each device in the daisy chain and prevents any further

data from being clocked into the input shift register. The serial

clock can be a continuous or a gated clock.

A continuous SCLK source can be used only if SYNC is held

low for the correct number of clock cycles. In gated clock mode,

a burst clock containing the exact number of clock cycles must

be used, and SYNC must be taken high after the final clock to

latch the data.

In any one daisy-chain sequence, do not mix writes to the DAC

daisy-chained parts must be either writes to the DAC registers

or writes to the control, clearcode, or software control register.

CONTROLLER

DATA IN

SYNC

SDIN

SCLK

DATA OUT

SERIAL CLOCK

CONTROL OUT

SDO

SYNC

SCLK

SDO

SYNC

SCLK

SDO

SDIN

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5760*

Figure 51. Daisy-Chain Block Diagram

Readback

The contents of all the on-chip registers can be read back via

the SDO pin. Table 7 outlines how the registers are decoded.

After a register has been addressed for a read, the next 24 clock

cycles clock the data out on the SDO pin. The clocks must be

applied while SYNC is low. When SYNC is returned high, the

SDO pin is placed in tristate. For a read of a single register, the

NOP function can be used to clock out the data. Alternatively,

if more than one register is to be read, the data of the first

that the second register to be read is being addressed. The SDO

pin must be enabled to complete a readback operation. The

SDO pin is enabled by default.

HARDWARE CONTROL PINS

Load DAC Function (LDAC)

After data has been transferred into the input register of the

DAC, there are two ways to update the DAC register and DAC

output. Depending on the status of both SYNC and LDAC, one

of two update modes is selected: synchronous DAC update or

asynchronous DAC update.

Synchronous DAC Update

In this mode, LDAC is held low while data is being clocked into

the input shift register. The DAC output is updated on the rising

edge of SYNC.

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