AD5700/AD5700-1

Data Sheet

Rev. A | Page 16 of 20

Table 7. Clock Configuration Options

XTAL_EN

CLK_CFG1

CLK_CFG0

CLKOUT

Description

1

0

0

No output

3.6864 MHz CMOS clock connected at XTAL1 pin

1

0

1

No output

1.2288 MHz CMOS clock connected at XTAL1 pin

1

1

0

No output

Internal oscillator enabled (AD5700-1 only)

1

1

1

1.2288 MHz output

Internal oscillator enabled, CLKOUT enabled (AD5700-1 only)

0

0

0

No output

Crystal oscillator enabled

0

0

1

3.6864 MHz output

Crystal oscillator enabled, CLKOUT enabled

0

1

0

1.8432 MHz output

Crystal oscillator enabled, CLKOUT enabled

0

1

1

1.2288 MHz output

Crystal oscillator enabled, CLKOUT enabled

POWER-DOWN MODE

The AD5700/AD5700-1 can be placed into power-down mode

by holding the RESET pin low. If using the internal reference, it

is recommended to tie the REF_EN pin to the RESET pin so

that it is also powered down. If the reference is not powered

down while RESET is low, the output voltage on the REF pin is

approximately 1.7 V until RESET is brought high again.

In this mode, the receive, transmit, and oscillator circuits are all

switched off, and the device consumes a typical current of 16 μA.

FULL DUPLEX OPERATION

Full duplex operation means that the modulator and demodula-

tor of the AD5700/AD5700-1 are enabled at the same time. This

is a powerful feature, enabling a self-test procedure of not only

the HART device but also the complete signal path between the

HART device and the host controller. This provides verification

that the local communications loop is functional. This increased

level of system diagnostics is useful in production self-test and

is advantageous in improving the application’s safety integrity

level (SIL) rating. The full duplex mode of operation is enabled by

connecting the DUPLEX pin to logic high.