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ADCMP671

Data Sheet

Rev. 0 | Page 14 of 16

APPLICATIONS INFORMATION

The ADCMP671 is a UV and OV monitor with a built-in 400 mV

reference that operates from 1.7 V to 5.5 V. The comparator is

0.275% accurate with a built-in hysteresis of 9.2 mV. The outputs

are open-drain, capable of sinking 40 mA.

COMPARATORS AND INTERNAL REFERENCE

There are two comparators inside the ADCMP671. The

comparator with its noninverting input connected to the INH

pin (and its inverting input connected internally to the 400 mV

reference) is for undervoltage detection, and the comparator

with its inverting input available through the INL pin (and its

noninverting input connected internally to the 400 mV reference)

is for overvoltage detection. The rising input threshold voltage of

the comparators is designed to be equal to that of the reference.

POWER SUPPLY

The ADCMP671 is designed to operate from 1.7 V to 5.5 V.

A 0.1 μF decoupling capacitor is recommended between VDD

and GND.

INPUTS

The comparator inputs are limited to the maximum VDD voltage

range. The voltage on these inputs can be more than VDD but never

more than the maximum allowed VDD voltage. When adding a

resistor string to the input, choose resistor values carefully because

the input bias current is in parallel with the bottom resistor of

the string. Therefore, choose the bottom resistor first to control

the error introduced by the bias current.

To minimize the number of external components use three

resistor dividers to program the UV and OV thresholds.

HYSTERESIS

To prevent oscillations at the output caused by noise or slowly

moving signals passing the switching threshold, each comparator

has a built-in hysteresis of approximately 8.9 mV.

VOLTAGE MONITORING SCHEME

When monitoring a supply rail, the desired nominal operating

voltage for monitoring is denoted by VM, IM is the nominal current

through the resistor divider, VOV is the overvoltage trip point,

and VUV is the undervoltage trip point.

Figure 34 illustrates the voltage monitoring input connection.

Three external resistors, RX, RY, and RZ, divide the positive voltage

for monitoring (VM) into the high-side voltage (VH) and low-

side voltage (VL). The high-side voltage is connected to the INH

pin, and the low-side voltage is connected to the INL pin.

INH

INL

VDD

GND

12V

400mV

ADCMP671

PWRGD

Figure 34. Undervoltage/Overvoltage Monitoring Configuration

To trigger an overvoltage condition, the low-side voltage (in this

case, VL) must exceed the 0.4 V threshold on the INL pin. The

low-side voltage, VL, is given by the following equation:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

Also,

Therefore, RZ, which sets the desired trip point for the overvoltage

monitor, is calculated using the following equation:

( )

()()

)

(

To trigger the undervoltage condition, the high-side voltage, VH,

must fall below the 0.4 V threshold on the INH pin. The high-

side voltage, VH, is given by the following equation:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

Because RZ is already known, RY can be expressed as follows:

( )

()() Z

−

)

(

When RY and RZ are known, RX is calculated using the following

equation:

( )

()

−

If VM, IM, VOV, or VUV changes each step must be recalculated.

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