ADCMP671

Data Sheet

Rev. 0 | Page 16 of 16

OUTLINE DIMENSIONS

*COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

13

4

5

2

6

2.90 BSC

1.60 BSC

2.80 BSC

1.90

BSC

0.95 BSC

0.10 MAX

*1.00 MAX

PIN 1

INDICATOR

*0.90

0.87

0.84

0.60

0.45

0.30

0.50

0.30

0.20

0.08

SEATING

PLANE

8°

4°

0°

Figure 36. 6-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

Temperature Range

Package Description

Package Option

Branding

ADCMP671-1YUJZ-RL7

−40°C to +125°C

6-Lead Thin Small Outline Transistor Package [TSOT]

UJ-6

LLS

©2011 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D10160-0-11/11(0)