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ADP1053ACPZ-R7 数据表(PDF) 74 Page - Analog Devices

部件名 ADP1053ACPZ-R7
功能描述  3-Channel Digital
PDF  84 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
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ADP1053ACPZ-R7 数据表(HTML) 74 Page - Analog Devices

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ADP1053
Data Sheet
Rev. A | Page 74 of 84
Table 113. Register 0xFE78—ACSNS Setting
Bits
Bit Name
R/W
Description
7
ACSNS flag included
in PGOOD
R/W
Setting this bit includes the ACSNS flag in the PGOOD_A and PGOOD_B flags. The debounce
time for this function is set with Bit 6.
6
Debounce of ACSNS
flag included in
PGOOD
R/W
This bit sets the debounce time of the ACSNS flag when it is included in the PGOOD_A and
PGOOD_B flags.
0 = 0 ms.
1 = 2.6 ms.
[5:2]
ACSNS threshold
R/W
These bits set the ACSNS threshold. This 4-bit value is compared with the four MSBs of the
ACSNS value register (Register 0xFED9). The hysteresis is 75 mV. When these bits are set to 0,
the ACSNS flag is always cleared. For more information, see the ACSNS Flag section.
These bits set the ACSNS flag debounce time.
Bit 1
Bit 0
Typical Debounce Time
0
0
0 ms
0
1
2.6 ms
1
0
10.4 ms
[1:0]
ACSNS flag
debounce time
R/W
1
1
100 ms
PSON REGISTERS
Table 114. Register 0xFE79—Channel A PSON Setting
Bits
Bit Name
R/W
Description
7
PSON_A polarity
R/W
Setting this bit inverts the polarity of the PSON_A pin signal when hardware PSON_A is used.
0 = normal mode. A high signal on the PSON_A pin turns on Channel A.
1 = inverted. A low signal on the PSON_A pin turns on Channel A.
6
Software PSON_A
R/W
When software PSON_A is used, setting this bit turns on Channel A.
These bits specify which signal or signals are used as the PSON_A control.
Bit 5
Bit 4
PSON_A Control Selection
0
0
Always on. Channel A is always on.
0
1
Hardware PSON_A. The PSON_A pin turns Channel A on and off.
1
0
Software PSON_A. Bit 6 turns Channel A on and off.
[5:4]
PSON_A control
hardware/software
selection
R/W
1
1
Software and hardware PSON_A. Both the PSON_A pin and Bit 6 must be set
to turn on Channel A.
These bits specify the delay from when the PSON_A signal is set to when the soft start of
Channel A begins.
Bit 3
Bit 2
Typical Delay Time
0
0
0 ms
0
1
50 ms
1
0
250 ms
[3:2]
PSON_A delay
R/W
1
1
1 sec
These bits specify the delay from when the PSON_A signal is cleared to when Channel A is
turned off.
Bit 1
Bit 0
Typical Delay Time
0
0
0 ms
0
1
50 ms
1
0
250 ms
[1:0]
PSOFF_A delay
R/W
1
1
1 sec



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