Data Sheet

ADRF6807

Rev. B | Page 21 of 36

Register 7—LO Divider Control

Register 7 controls the LO path main divider settings as well as the LO output path divider setting. Table 5 indicates how to program this

register to achieve the specified divider mode.

DIVIDER

SELECT

DIV A/B

CONTROL

OUTPUT DIV

CONTROL

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DIVS1

DB6

DB5

DB4 DB3 DB2 DB1 DB0

0

0

DIVAB1 DIVAB0

DIVS0 ODIV1 ODIV0

0

C3(1) C2(1) C1(1)

DIVAB1

0

0

2 (DEFAULT)

3

DIVIDE RATIO

CONTROL BITS

DIVAB0

0

1

1

1

4 (NOT VALID FOR DIVB)

5 (NOT VALID FOR DIVB)

0

1

DIVS1

0

0

DIV B ONLY (DEFAULT)

DIV A FOLLOWED BY ÷ 2

DIVIDE RATIO

DIVS0

0

1

1

1

DIV A FOLLOWED BY ÷ 4

DIV A FOLLOWED BY ÷ 8

0

1

ODIV1

0

0

4 (DEFAULT)

4

DIVIDE RATIO

ODIV0

0

1

1

1

6

8

0

1

00

0

0

0

00

0

00

0

0

Figure 40. LO Divider Control Register (R7)

LO DIVIDER PROGRAMMING

Table 5. Main Divider (Only Divide Ratios and Combinations Specified Are Guaranteed)

Divider Cascade

LO Divider

Ratio

Divide-by-2 to Divide-by-5

Divide-by-2, Divide-by-4, or

Divide-by-8

Quadrature

Divide-by-2

Register 7,

DB[9:6]

700 to 1050

4

2800 to 4200

2

Not used

2

00 00

Table 6. Output Divider

Output Divider Ratio

Register 7, DB[5:4]

350 to 525

8

2800 to 4200

11

466.67 to 700

6

2800 to 4200

10

700 to 1050

4

2800 to 4200

01

PROGRAMMING EXAMPLE

For example, internal LO frequency = 700 MHz. This can be accomplished with the VCO/PLL frequency at 2800 MHz and an LO divide

ratio of 4. The choice of output divider ratio of 8 gives an output frequency of 350 MHz. To achieve this combination, a binary code of

00 00 11 should be programmed into DB[9:4] of Register 7.