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ADRF6704ACPZ-R7 数据表(PDF) 4 Page - Analog Devices |
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ADRF6704ACPZ-R7 数据表(HTML) 4 Page - Analog Devices |
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4 / 36 page  ADRF6704 Data Sheet Rev. 0 | Page 4 of 36 Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE CHARACTERISTICS REFIN, MUXOUT pins REFIN Input Frequency 11 160 MHz REFIN Input Capacitance 4 pF Phase Detector Frequency 22 40 MHz MUXOUT Output Level Low (lock detect output selected) 0.25 V High (lock detect output selected) 2.7 V MUXOUT Duty Cycle 50 % CHARGE PUMP Charge Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1000 μA 500 μA Output Compliance Range 1 2.8 V PHASE NOISE (FREQUENCY = 2500 MHz, fPFD = 38.4 MHz) Closed loop operation (see Figure 35 for loop filter design) 10 kHz offset −100.9 dBc/Hz 100 kHz offset −100 dBc/Hz 1 MHz offset −126 dBc/Hz 10 MHz offset −148.3 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.37 °rms Reference Spurs fPFD/2 −111 dBc fPFD −87.3 dBc fPFD × 2 −93.6 dBc fPFD × 3 −92.8 dBc fPFD × 4 −98.2 dBc PHASE NOISE (FREQUENCY = 2700 MHz, fPFD = 38.4 MHz) Closed loop operation (see Figure 35 for loop filter design) 10 kHz offset −97.7 dBc/Hz 100 kHz offset −97.6 dBc/Hz 1 MHz offset −126.1 dBc/Hz 10 MHz offset −148.4 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.46 °rms Reference Spurs fPFD/2 −110.4 dBc fPFD −89.9 dBc fPFD × 2 −92 dBc fPFD × 3 −89.9 dBc fPFD × 4 −94.5 dBc PHASE NOISE (FREQUENCY = 2900 MHz, fPFD = 38.4 MHz) Closed loop operation (see Figure 35 for loop filter design) 10 kHz offset −92.3 dBc/Hz 100 kHz offset −96.4 dBc/Hz 1 MHz offset −125.2 dBc/Hz 10 MHz offset −148.5 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.62 °rms Reference Spurs fPFD/2 −110.7 dBc fPFD −90.9 dBc fPFD × 2 −89.8 dBc fPFD × 3 −92.1 dBc fPFD × 4 −93.7 dBc RF OUTPUT HARMONICS Measured at RFOUT, frequency = 2700 MHz Second harmonic −44.4 dBc Third harmonic −76.7 dBc LO INPUT/OUTPUT LOP, LON Output Frequency Range Divide by 2 circuit in LO path enabled 2500 2900 MHz Divide by 2 circuit in LO path disabled 5000 5800 MHz LO Output Level at 2700 MHz 1× LO mode, into a 50 Ω load, LO buffer enabled −2 dBm LO Input Level Externally applied 2× LO, PLL disabled 0 dBm LO Input Impedance Externally applied 2× LO, PLL disabled 50 Ω |
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