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Data Sheet

ADP5024

Rev. A | Page 17 of 28

POWER MANAGEMENT UNIT

The ADP5024 is a micropower management unit (microPMU)

combing two step-down (buck) dc-to-dc convertors and one

low dropout linear regulator (LDO). The high switching frequency

and tiny 24-lead LFCSP package allow for a small power manage-

ment solution.

To combine these high performance regulators into the

microPMU, there is a system controller allowing them to

operate together.

The buck regulators can operate in forced PWM mode if the

MODE pin is at a logic level high. In forced PWM mode, the

buck switching frequency is always constant and does not

change with the load current. If the MODE pin is at logic level

low, the switching regulators operate in automatic PWM/PSM

mode. In this mode, the regulators operate at a fixed PWM

frequency when the load current is above the PSM current

threshold. When the load current falls below the PSM current

threshold, the regulator in question enters PSM, where the

switching occurs in bursts. The burst repetition rate is a

function of the current load and the output capacitor value.

This operating mode reduces the switching and quiescent

current losses. The automatic PWM/PSM mode transition is

controlled independently for each buck regulator. The two

bucks operate synchronized to each other.

The ADP5024 has individual enable pins (EN1 to EN3) that

control the activation of each regulator. The regulators are

activated by a logic level high applied to the respective EN pin,

wherein EN1 controls BUCK1, EN2 controls BUCK2, and EN3

controls the LDO.

Regulator output voltages are set through external resistor

dividers or can be optionally factory programmed to default

values (see the Ordering Guide section).

When a regulator is turned on, the output voltage ramp rate is

controlled though a soft start circuit to avoid a large inrush

current due to the charging of the output capacitors.

Thermal Protection

In the event that the junction temperature rises above 150°C,

the thermal shutdown circuit turns off all of the regulators.

Extreme junction temperatures can be the result of high current

operation, poor circuit board design, or high ambient tempera-

ture. A 20°C hysteresis is included so that when thermal shutdown

occurs, the regulators do not return to operation until the on-chip

temperature drops below 130°C. When emerging from thermal

shutdown, all regulators restart with soft start control.

Undervoltage Lockout

To protect against battery discharge, undervoltage lockout

(UVLO) circuitry is integrated in the system. If the input

voltage on VIN1 drops below a typical 2.15 V UVLO threshold,

all channels shut down. In the buck channels, both the power

switch and the synchronous rectifier turn off. When the voltage

on VIN1 rises above the UVLO threshold, the part is enabled

once more.

Alternatively, the user can select device models with a UVLO

set at a higher level, suitable for USB applications. For these

models, the device reaches the turn off threshold when the

input supply drops to 3.65 V typical.

In case of a thermal or UVLO event, the active pull-downs (if

factory enabled) are enabled to discharge the output capacitors

quickly. The pull-down resistors remain engaged until the thermal

fault event is no longer present or the input supply voltage falls

below the VPOR voltage level. The typical value of VPOR is approx-

imately 1 V.

Enable/Shutdown

The ADP5024 has an individual control pin for each regulator.

A logic level high applied to the ENx pin activates a regulator

whereas a logic level low turns off a regulator.

Figure 46 shows the regulator activation timings for the

ADP5024 when all enable pins are connected to AVIN. Also

shown is the active pull-down activation.

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