SSM2518CBZ-R7 datasheet(36/48 Pages) AD

36 / 48 page

SSM2518

Data Sheet

Rev. A | Page 36 of 48

DRC CONTROL 1 REGISTER

Address: 0x0A, Reset: 0x7C, Name: DRC_Control_1

Table 23. Bit Descriptions for DRC_Control_1

Bits

Bit Name

Settings

Description

Reset

Access

RESERVED

Reserved.

0x0

PRE_VOL

DRC Placement. This determines the placement of the DRC block in the

signal chain. When placed before the volume control, the thresholds are

relative to the input signal. When placed after the volume control, the

thresholds are relative to the output signal level. All thresholds are 6 dB

higher when placed after the volume control.

0x1

DRC operates after the volume control

DRC operates before the volume control

LIM_EN

Limiter Enable. With the limiter enabled, the DRC_LT threshold (Bits[7:4] in

0x1

Limiter disabled

Limiter enabled

COMP_EN

Compressor Enable. With the compressor enabled, the DRC_CT and

DRC_SMAX thresholds (Bits[3:0] in Register 0x0C and Bits[7:4] in

0x1

Compressor disabled

Compressor enabled

EXP_EN

Expander Enable. With the expander enabled, the DRC_ET and DRC_SMIN

threshold values (Bits[7:4] in Register 0x0D and Bits[3:0] in Register 0x0E)

must be set.

0x1

Expander disabled

Expander enabled

NG_EN

Noise Gate Enable. With the noise gate enabled, the DRC_NT threshold

value (Bits[3:0] in Register 0x0D) must be set.

0x1

Noise gate disabled

Noise gate enabled

[1:0]

DRC_EN

Master DRC Enable. This must be enabled for any of the DRC features to

function.

0x0

DRC disabled

Left channel DRC enabled

Right channel DRC enabled

Left and right channel DRC enabled

SSM2518CBZ-R7 数据表(PDF) 36 Page - Analog Devices

SSM2518CBZ-R7 数据表(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载