SSM2518CPZ-R7 datasheet(26/48 Pages) AD

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SSM2518

Data Sheet

Rev. A | Page 26 of 48

SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER

Address: 0x00, Reset: 0x05, Name: Reset_Power_Control

Table 13. Bit Descriptions for Reset_Power_Control

Bits

Bit Name

Settings

Description

Reset

Access

S_RST

Software Reset. Write 1 to reset all internal blocks, including I2C registers,

to their initial state.

0x0

Normal operation

Software reset

RESERVED

Reserved.

0x0

NO_BCLK

Bit Clock Source Selection. Either the MCLK or BCLK pin can be routed

internally to the bit clock.

0x0

BCLK pin used as bit clock source. Typical configuration.

MCLK pin used as bit clock source. No BCLK pin connection is needed.

[4:1]

MCS

Master Clock Select. This must match the ratio between the input MCLK

frequency and the audio sample rate, as shown in Table 11.

0x2

0000

64 × fS

0001

128 × fS

0010

256 × fS

0011

384 × fS

0100

512 × fS

0101

768 × fS

0110

100 × fS

0111

200 × fS

1000

400 × fS

1001

Reserved

SPWDN

Software Master Power-Down. This places all blocks, except the I2C

interface, into a low power state.

0x1

Normal operation

Software master power-down

SSM2518CPZ-R7 数据表(PDF) 26 Page - Analog Devices

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