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LTM4607 数据表(PDF) 23 Page - Linear Technology |
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LTM4607 数据表(HTML) 23 Page - Linear Technology |
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23 / 28 page ![]() LTC3780 23 3780fe APPLICATIONS INFORMATION Double-check the TJ in the MOSFET with 70°C ambient temperature: TJ = 70°C + 1.94W • 40°C/W = 147.6°C The maximum power dissipation of switch B occurs in buck mode. Assuming a junction temperature of TJ = 80°C with ρ80°C = 1.2, the power dissipation at VIN = 18V is: PB,BUCK = 18 – 12 18 •5 2 •1.2•0.009 = 90mW Double-check the TJ in the MOSFET at 70°C ambient temperature: TJ = 70°C + 0.09W • 40°C/W = 73.6°C The maximum power dissipation of switch C occurs in boost mode. Assuming a junction temperature of TJ = 110°C with ρ110°C = 1.4, the power dissipation at VIN = 5V is: PC,BOOST = 12 – 5 ( )•12 5 2 •5 2 •1.4•0.009 + 2•12 3 • 5 5 •150p • 400k = 1.27W Double-check the TJ in the MOSFET at 70°C ambient temperature: TJ = 70°C + 1.08W • 40°C/W = 113°C The maximum power dissipation of switch D occurs in boost mode when its duty cycle is higher than 50%. Assuming a junction temperature of TJ = 100°C with ρ100°C = 1.35, the power dissipation at VIN = 5V is: PW D BOOST , = ⎛ ⎝⎜ ⎞ ⎠⎟ = 5 12 12 5 5 1 35 0 009 0 73 2 Double-check the TJ in the MOSFET at 70°C ambient temperature: TJ = 70°C + 0.73W • 40°C/W = 99°C CIN is chosen to filter the square current in buck mode. In this mode, the maximum input current peak is: IA IN PEAK MAX BUCK ,( , ) % . =+ ⎛ ⎝⎜ ⎞ ⎠⎟ = 51 29 2 57 A low ESR (10mΩ) capacitor is selected. Input voltage ripple is 57mV (assuming ESR dominate ripple). COUT is chosen to filter the square current in boost mode. In this mode, the maximum output current peak is: IOUT PEAK MAX BOOST ,( , ) % . =+ ⎛ ⎝⎜ ⎞ ⎠⎟ = 12 5 51 11 2 10 6 6A A low ESR (5mΩ) capacitor is suggested. This capacitor will limit output voltage ripple to 53mV (assuming ESR dominate ripple). PC Board Layout Checklist The basic PC board layout requires a dedicated ground plane layer. Also, for high current, a multilayer board provides heat sinking for power components. • The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. • Place CIN, switch A, switch B and D1 in one com- pact area. Place COUT, switch C, switch D and D2 in one compact area. One layout example is shown in Figure 10. GND VOUT COUT L RSENSE 3780 F10 QD QC QB QA SW2 SW1 D1 D2 VIN CIN LTC3780 CKT Figure 10. Switches Layout |
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