MPC8569E datasheet(49/127 Pages) FREESCALE

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DDR2 and DDR3 SDRAM Controller

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

The following figure shows the DDR2 and DDR3 SDRAM interface input timing diagram.

Figure 8. DDR2 and DDR3 SDRAM Interface Input Timing Diagram

Tolerated Skew for MDQS—MDQ/MECC

tDISKEW

——

800 MHz data rate

–425

425

667 MHz data rate

–510

510

533 MHz data rate

–635

635

400 MHz data rate

–885

885

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is

captured with MDQS[n]. This must be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

determined by the following equation: tDISKEW =±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

3. Parameters tested in DDR2 mode are to 400, 533, 667, and 800 MHz data rates and in DDR3 mode to 667 and 800 MHz data

rates.

Table 19. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications3 (continued)

At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3

Parameter

Symbol

Min

Max

Unit

Note

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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