MCM69C232

8

MOTOROLA FAST SRAM

INTERRUPT BIT DEFINITIONS

Bit 0:

1 = Enable interrupt on insert with full entry

queue

Bit 1:

1 = Enable interrupt on insert with full table

Bit 2:

1 = Enable interrupt on completion of

CHECK–FOR–VALUE instruction

Bit 3:

1 = Enable interrupt on completion of

INITIALIZE–TABLE instruction

Bit 4:

1 = Enable interrupt on failed attempt to enter

fast entry mode

Bit 5:

1 = Enable interrupt on CAM table reaching

almost–full point

Bit 6:

1 = Enable interrupt on fast read with non–empty

queue

Bit 7:

1 = Enable interrupt on illegal instruction

INSTRUCTION SET DETAILS

The MCM69C232 is prepared for match operations by

writing to data and instruction registers via the control port. In

the general case, required data is loaded into I/O registers

0 – 3, then an instruction is issued by writing an operation

code to the instruction register. As a result of running an

instruction, the CAM table can be modified, bit(s) can be set

in the flag register, error codes can be returned in the error

code register, and an interrupt can be generated if enabled.

For a particular condition to generate an interrupt, the inter-

rupt register bit specific to that condition must be set. The

user should verify that the operation–complete bit of the flag

register is set before executing the next instruction, if the

instruction just executed is one that modifies I/O registers.

Table 1. MCM69C232 Operation Summary

Operation

Description

OP Code (Base 16)

INSERT VALUE

Loads a new entry into the CAM table

0000 or 000F

DELETE VALUE

Removes an entry from the CAM table

0001 or 000E

CHECK FOR VALUE

Runs a match cycle via the control port

0006

INITIALIZE TABLE

Prepares CAM table for matching

000B

FAST ENTRY MODE

Selects entry mode suited for initial CAM table load

0004

BUFFERED ENTRY MODE

Selects entry mode suited for simultaneous loading

and matching

0005

SET ATM MODE

Enter mode that provides concurrent VPC/VCC

search

0008

RETURN ENTRY COUNT

Determines number of entries in CAM

0003

SET GLOBAL MASK REGISTER

Determines match bits to be checked in a match

operation

0002 or 000D

SET ALMOST–FULL POINT

Defines CAM almost full condition

0007

SET FAST–READ REGISTER

Defines table entry that is output by the fast read

operation

0009

FAST READ

Outputs one CAM table entry

000A

INSERT VALUE

This instruction is used to load a new match/output value

into the CAM. The contents of I/O registers 0 – 3 are con-

catenated, with bit 15 of register 3 as the most significant bit,

and bit 0 of register 0 as the least significant bit.

If the MCM69C232 is running in buffered entry mode, the

resulting 64 bit value is written to the first available location in

the entry queue, and is immediately available for matching. If

a buffered insert–value instruction is attempted when the

entry queue is full (indicated by bit 5 of the flag register = 1),

no value is written, an error code of FFF816 is returned in the

error code register, and the error–condition flag (bit 7) is set

in the flag register. An interrupt is generated, if enabled by bit

0 of the interrupt register being set.

If the MCM69C232 is running in fast entry mode, the con-

catenated 64 bit value is written directly to the CAM array. If

an insert–value instruction is attempted when in fast entry

mode and the table is full, no value is written, an error code of

FFF916 is returned in the error code register, and the error–

condition flag (bit 7) is set in the flag register. (The table–full

condition is indicated by bit 6 of the flag register being set.)

An interrupt is generated, if enabled by bit 1 of the interrupt

register being set.

Only one entry is allowed for a given match pattern. If an

entry is made in the table that duplicates an existing match

pattern, it will overwrite the entry already in the CAM table, if

the CAM is in buffered entry mode. The user must ensure

that no entries with the same match pattern are inserted in

fast entry mode.

DELETE VALUE

This instruction is used to remove a match/output value

from the CAM. The contents of I/O registers 0 – 3 are con-

catenated, with bit 15 of register 3 as the most significant bit,

and bit 0 of register 0 as the least significant bit. The bits that

have a 0 in the corresponding bit of the global–mask register

are used to find a matching entry in the CAM table. If such an

entry is found, it is invalidated. Note that any bit that is not a

match bit as defined by the mask register is ignored for this

operation. The operation of the MCM69C232 guarantees

that no more than one matching entry can exist in the table,