SP690T/S/R DS/10

SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory

© Copyright 2000 Sipex Corporation

4

SPECIFICATIONS (continued)

V

T

NOTE 1: The following are tested at V

functionality, logic input leakage, PFI functionality, and the RESET and RESET states. The state of

RESET or RESET and PFO is tested at V

NOTE 2: Tested V

NOTE 3: Leakage current into the battery is tested under the following worst-case conditions: V

CC

= 5.5V, V

NOTE 4: "-" equals the battery-charging current, "+" equals the battery-discharging current.

NOTE 5: When V

V

NOTE 6: When V

switch threshold, V

NOTE 7: V

V

Switchover back to V

SP804_ and SP805_ RESET goes LOW). Switchover occurs 200ms prior to reset.

NOTE 8: The reset threshold tolerance is wider for V

10mV typical hysteresis, which prevents internal oscillation.

NOTE 9: SP690_ and SP802_ devices only.

NOTE 10: SP804_ and SP805_ devices only.

NOTE 11: The leakage current into or out of the RESET pin is tested with RESET asserted (RESET

output high impedance).